Found 3 query results that match vJ-2014.09 SP3
-
- Formality and Formality Ultra
Verifies the toughest designs synthesized with DC
Overview
Formality® is an equivalence-checking (EC) solution that uses formal, static techniques to determine if two versions of a design are functionally equivalent.
The size and complexity of today’s designs, cou.....
- Language : english Authorization: Retail Freshtime：2015-03-17 Size: 1DVD
-
- TetraMAX ATPG
Automatic Test Pattern Generation
Overview
TetraMAX® ATPG automatically generates high quality manufacturing test patterns. It’s the only ATPG solution optimized for a wide range of test methodologies and integrated with Synopsys’ patented DFTMAX™ and DFTMAX Ultra, the leading t.....
- Language : english Authorization: Retail Freshtime：2015-03-17 Size: 1CD
-
-
Comprehensive Place and Route System
Overview
IC Compiler is the leading place and route system. A single, convergent, chip-level physical implementation tool, it includes flat and hierarchical design planning, placement, clock tree synthesis, routing and optimization, manufacturability, and low-.....
- Language : english Authorization: Retail Freshtime：2015-03-17 Size: 1DVD